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datasheet real-time clock with batte ry backed non-volatile ram IDT1338 idt? real-time clock with battery backed non-volatile ram 1 IDT1338 rev s 111214 general description the IDT1338 is a serial real-time clock (rtc) device that consumes ultra-low power and provides a full binary-coded decimal (bcd) clock/calendar with 56 bytes of battery backed non-volatile static ram. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the clock operates in either the 24-hour or 12-hour format with am/pm indicator. the end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. access to the clock/calendar registers is provided by an i 2 c interface capable of operating in fast i 2 c mode. built-in power-sense circuitry detects power failures and automatically switches to the backup supply, maintaining time and date operation. applications ? telecom (routers, switches, servers) ? handheld (gps, point of sale pos terminals) ? consumer electronics (set-top box, digital recording, network applications, digital photo frames) ? office (fax/printers, copiers) ? medical (glucometer, medicine dispensers) ? others (thermostats, vendi ng machines, modems, utility meters) features ? real-time clock (rtc) counts seconds, minutes, hours, day, date, month, and year with leap-year compensation valid up to 2100 ? 56-byte battery-backed non volatile ram for data storage ? fast mode i 2 c serial interface ? automatic power-fail detect and switch circuitry ? programmable square-wave output ? packaged in 8-pin msop, 8-pin soic, or 16-pin soic (surface-mount package with an integrated crystal) ? industrial temperature range (-40c to +85c) block diagram vcc gnd v bat scl sda crystal inside package for 16-pin soic only x1 x2 1 hz/4.096 khz/ 8.192 khz/32.768 khz sqw/out power control i 2 c interface 32.768 khz oscillator and divider control logic mux/ buffer clock, calendar counter 56 byte ram 1 byte control 7 bytes buffer
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 2 IDT1338 rev s 111214 pin assignment (8-pin msop/8-pin soic) pin assignment (16-pin soic) pin descriptions x1 scl sqw/out gnd vcc 1 2 3 4 8 7 6 5 sda x2 v bat idt 1338 16 1 15 2 14 3 13 4 5 6 7 8 9 10 12 11 scl vcc nc nc nc nc nc nc nc nc nc nc sda gnd sqw/out v bat idt 1338c pin number pin name pin description/function 8msop, 8soic 16soic 1 ? x1 connections for standard 32.768 khz quartz cryst al. the internal oscillator circuitry is designed for operation with a crystal having a specified l oad capacitance (cl) of 12.5 pf. an external 32.768 khz oscillator can also drive the IDT1338. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is left floating. 2?x2 314v bat backup supply input for lithium coin cell or other energy source. battery voltage must be held between the minimum and maximum limits for proper operation. diodes placed in series between the backup source and the v bat pin may prevent proper operation. if a backup supply is not required, v bat must be connected to ground. 4 15 gnd connect to ground. 5 16 sda serial data input/output. sda is the input/output pin for the i 2 c serial interface. it is an open-drain output and requires an external pull-up resistor (2 kohm typical). 6 1 scl serial clock input. scl is used to synchronize data movement on the serial interface. it is an open-drain output and requires an extern al pull-up resistor (2 kohm typical) 7 2 sqw/out square-wave/output driver. when enabled and the sqwe bit set to 1, the sqw/out pin outputs one of four square-wave frequencies (1 hz, 4 khz, 8 khz, 32 khz). it is an open drain output and requires an external pull-up resistor (10k ohm typical). operates when the device is powered with vcc or v bat . 83v cc device power supply. when voltage is applied within specified limits, the device is fully accessible by i 2 c and data can be written and read. ? 4 - 13 nc no connect. these pins are unused and mu st be connected to ground for proper operation.
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 3 IDT1338 rev s 111214 typical operating circuit detailed description the following sections discuss in detail the oscillator block, power control block, clock/calendar register block and serial i 2 c block. oscillator block selection of the right crystal, correct load capacitance and careful pcb layout are important for a stable crystal oscillator. due to the optimization for the lowest possible current in the design for these oscillators, losse s caused by parasitic currents can have a significant impact on the overall oscillator performance. extra care needs to be taken to maintain a certain quality and cleanliness of the pcb. crystal selection the key parameters when selecting a 32 khz crystal to work with IDT1338 rtc are: ? recommended load capacitance ? crystal effective series resistance (esr) ? frequency tolerance effective load capacitance please see diagram below for effective load capacitance calculation. the effective load capacitance (cl) should match the recommended load capacitance of the crystal in order for the crystal to oscilla te at its specified parallel resonant frequency with 0ppm frequency error. in the above figure, x1 and x2 are the crystal pins of our device. cin1 and cin2 are the internal capacitors which include the x1 and x2 pin capacitance. cex1 and cex2 are the external capacitors that are needed to tune the crystal frequency. ct1 and ct2 are the pcb trace capacitances between the crystal and the device pins. cs is the shunt capacitance of the crystal (as specified in the crystal manufacturer's datasheet or measured using a network analyzer). note : IDT1338csri integrates a standard 32.768 khz crystal in the package and contributes an additional frequency error of 10ppm at nominal v cc (+3.3 v) and t a = +25c. cpu x1 x2 v cc sqw/out v bat gnd sda scl crystal IDT1338 + - v cc 2k 2k v cc v cc 10k
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 4 IDT1338 rev s 111214 esr (effective series resistance) choose the crystal with lower esr. a low esr helps the crystal to start up and stabilize to the correct output frequency faster compared to high esr crystals. frequency tolerance the frequency tolerance for 32 khz crystals should be specified at nominal temperature (+25c) on the crystal manufacturer datasheet. the crystals used with IDT1338 typically have a frequency tolerance of +/-20ppm at +25c. specifications for a typical 32khz crystal used with our device are shown in the table below. pcb design consideration ? signal traces between idt device pins and the crystal must be kept as short as possible. this minimizes parasitic capacitance and sensitivity to crosstalk and emi. note that the trace capacitances play a role in the effective crystal load capacitance calculation. ? data lines and frequently switching signal lines should be routed as far away from the crystal connections as possible. crosstalk from these signals may disturb the oscillator signal. ? reduce the parasitic capacitance between x1 and x2 signals by routing them as far apart as possible. ? the oscillation loop current flows between the crystal and the load capacitors. this signal path (crystal to cl1 to cl2 to crystal) should be kept as short as possible and ideally be symmetric. the ground connections for both capacitors should be as cl ose together as possible. never route the ground connection between the capacitors all around the crystal, because this long ground trace is sensitive to crosstalk and emi. ? to reduce the radiation / co upling from oscillator circuit, an isolated ground island on the gnd layer could be made. this ground island can be connected at one point to the gnd layer. this helps to keep noise generated by the oscillator circuit locally on this separated island. the ground connections for the load capacitors and the oscillator should be connected to this island. pcb layout pcb assembly, soldering and cleaning board-assembly production process and assembly quality can affect the performance of the 32 khz oscillator. depending on the flux material used, the soldering process can leave critical residues on the pcb surface. high humidity and fast temperature cycles that cause humidity condensation on the printed circuit board can create process residuals. these process residuals cause the insulation of the sensitive o scillator signal lines towards each other and neighboring signals on the pcb to decrease. high humidity can lead to moisture condensation on the surface of the pcb and, together with process residuals, reduce the surface resistivity of the board. flux residuals on the board can cause leakage current paths, especially in humid environments. thorough pcb cleaning is therefore highly recommended in order to achieve maximum performance by removing flux residuals from the board after assembly. in general, reduction of losses in the oscillator circuit leads to better safe ty margin and reliability. parameter symbol min typ max units nominal freq. f o 32.768 khz series resistance esr 110 k ? load capacitance c l 12.5 pf
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 5 IDT1338 rev s 111214 power control a precise, temperature-compensated voltage reference and a comparator circuit provides power-control function that monitors the v cc level. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v bat , the device power is switched from v cc to v bat when v cc drops below v pf . if v pf is greater than v bat , the device power is switched from v cc to v bat when v cc drops below v bat . the registers are maintained from the v bat source until v cc is returned to nominal levels (table 1). after v cc returns above v pf , read and write access is allowed after t rec (see the ?power-up/down timing? diagram). table 1. power control power-up/down timing table 2. power-up/down characteristics ambient temperature -40 to +85 ? c note 1 : this delay applies only if the oscilla tor is running. if the oscillator is disabled or stopped, no power-up delay occurs. note 2 : measured at typ vbat level. supply condition read/write access powered by v cc < v pf , v cc < v bat no v bat v cc < v pf , v cc > v bat no v cc v cc > v pf , v cc < v bat ye s v cc v cc > v pf , v cc > v bat ye s v cc parameter symbol conditions min. typ. max. units recovery at power-up t rec (see note 1) 2 ms v cc fall time; v pf(max) to v pf(min) t vccf IDT1338-18, (see note 2) 3 ms IDT1338-31, (see note 2) 3 ms v cc rise time; v pf(min) to v pf(max) t vccr 0s
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 6 IDT1338 rev s 111214 rtc and ram address map the address map for the rtc and ram registers shown in table 3. the rtc registers and control register are located in address locations 00h to 07h the ram registers are located in address locations 08h to 3fh. during a multibyte access, when the register pointer reaches 3fh (the end of ram space) it wraps around to location 00h (the beginning of the clock space). on an i 2 c start, stop, or register pointer incrementing to location 00h, the current time and date is transferred to a second set of registers. the time and date in the secondary registers are read in a multibyte data transfer, while the clock continues to run. this eliminates the need to re-read the registers in case of an update of the main registers during a read. table 3. rtc and ram address map note : bits listed as ?0? should always be written and read as 0. clock and calendar table 3 shows the address map of the rtc registers. the time and date information is obtained by reading the appropriate register bytes. the time and calendar are set or initialized by writing the appro priate register bytes. the contents of the time and calendar registers are in the bcd format. bit 7 of register 0 is the clock halt (ch) bit. when this bit is set to 1, the oscilla tor is disabled. when cleared to 0, the oscillator is enabled. the clock can be halted whenever the timekeeping functions are not required, which decreases v bat current. the day-of-week register increments at midnight. values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. when reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop, and when the address pointer rolls over to zero. the countdown chain is reset whenever the seconds register is written. write transfers occurs on the acknowledge pulse from the device. to avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within one second. if enabled, the 1 hz square-wave output transitions high 500 ms after the seconds data transfer, provided the oscillator is already running. note that the initial power-on state of all registers, unless otherwise specified, is not defined. therefore, it is important to enable the oscillator (ch = 0) during initial configuration. the IDT1338 runs in either 12-hour or 24-hour mode. bit 6 of the hours register is defined as the 12-hour or 24-hour mode-select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am /pm bit, with logic high address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h ch 10 seconds seconds seconds 00 - 59 01h 0 10 minutes minutes minutes 00 - 59 02h 0 12/24 am /pm 10 hour hour hours 1 - 12 + am/pm 00 - 23 10 hour 03h00000 day day 1 - 7 04h 0 0 10 date date date 01 - 31 05h 0 0 0 10 month month month 01 - 12 06h 10 year year year 00 - 99 07h out 0 osf sqwe 0 0 rs1 rs0 control 08h - 3fh ram 56 x 8 00h - ffh
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 7 IDT1338 rev s 111214 being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20?23 hours). if the 12/24 -hour mode select is changed, the hours register must be re-initialized to the new format. on an i 2 c start, the current time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock continues to run. this eliminates the need to re-read the registers in case of an update of the main registers during a read. table 4. control register (07h) the control register controls th e operation of the sqw/out pin and provides oscillator status. bit 7: output control (out). controls the output level of the sqw/out pin w hen the square-wave output is disabled. if sqwe = 0, the logic level on the sqw/out pin is 1 if out = 1; it is 0 if out = 0. bit 5: oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time period and can be used to judge the validity of the clock and cale ndar data. this bit is edge triggered, and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a st op condition. the following are examples of conditions that may cause the osf bit to be set: 1) the first time power is applied. 2) the voltage present on vcc and vbat ar e insufficient to support oscillation. 3) the ch bit is set to 1, disabling the oscillator. 4) external influences on the crystal (i.e., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0. this bit ca n only be written to logic 0. attempting to write osf to logic 1 leaves the value unchanged. bit 4: square-wave enable (sqwe). when set to logic 1, this bit enables the oscillator output to operate with either vcc or v bat applied. the frequency of the square-wave outpu t depends upon the value of the rs0 and rs1 bits. bits 1 and 0: rate select (rs1 and rs0). these bits control the frequency of the square-wave output when the square-wave output has been enabled. the table below lists the square-wa ve frequencies that can be selected with the rs bits. table 5. square wave output bit #bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 name out 0 osf sqwe 0 0 rs1 rs0 por10110011 out rs1 rs0 sqw output sqwe x00 1 hz 1 x 0 1 4.096 khz 1 x 1 0 8.192 khz 1 x 1 1 32.768 khz 1 0xx 0 0 1xx 1 0
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 8 IDT1338 rev s 111214 i 2 c serial data bus the IDT1338 supports the i 2 c bus protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are referred to as slaves. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the IDT1338 operates as a slave on the i 2 c bus. within the bus specifications, a standard mode (100 khz maximum clock rate) and a fast mode (400 khz maximum clock rate) are defined. the IDT1338 works in both modes. connections to the bus are made via the open-drain i/o lines sda and scl. the following bus protocol has been defined (see the ?data transfer on i 2 c serial bus? figure): ? data transfer may be initiate d only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the cl ock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiate d with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited, and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. timeout: timeout is where a slave device resets its interface whenever clock goes low for longer than the timeout, which is typically 35 msec. this added logic deals with slave errors and recovering from those errors. when timeout occurs, the slave interfac e should re-initialize itself and be ready to receive a communication from the master, but it will expect a start prior to any new communication.
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 9 IDT1338 rev s 111214 data transfer on i 2 c serial bus depending upon the state of the r/w bit, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data is transferred with the most significant bit (msb) first. 2) data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. this is followed by the slave transmitting a number of data bytes. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. data is transferred with the most significant bit (msb) first. the IDT1338 can operate in the following two modes: 1) slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit (see the ?data write?slave receiver mode? figure). the slave address byte is the first byte received after the start condition is generated by the master. the slave address byte contains the 7-bit IDT1338 address, which is 1101000, followed by the direction bit (r/w ), which is 0 for a write. after receiving and decoding the slave address byte the slave outputs an acknowledge on the sda line. after the IDT1338 acknowledges the slave address + write bit, the master transmits a register address to the IDT1338. this sets the register pointer on the IDT1338, with the IDT1338 acknowledging the transfer. the master may then transmit zero or more bytes of data, with the IDT1338 acknowledging each byte received. the address pointer increments after each data byte is transferred. the master generates a stop condition to terminate the data write. 2) slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the IDT1338 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer (see the ?data read?slave transmitter mode? figure). the slave address byte is the first byte received after the start condition is generated by the master. the slave address byte contains the 7-bit IDT1338 address, which is 1101000, followed by the direction bit (r/w ), which is 1 for a read. after receiving and decoding the slave address byte the slave outputs an acknowledge on the sda line. the IDT1338 then begins to transmit data starting with the register address pointed to by
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 10 IDT1338 rev s 111214 the register pointer. if the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. the address pointer is incremented after each byte is transferred. the IDT1338 must receive a ?not acknowledge? to end a read. data write ? slave receiver mode data read (from current pointer location) ? sla ve transmitter mode data read (write pointer, then read) ? slave receive and transmit
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 11 IDT1338 rev s 111214 handling, pcb layout, and assembly the IDT1338 package contains a quartz tuning-fork crystal. pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avioded. ultarsonic cleaning equipment should be avioded to prevent damage to the crystal. avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. all nc (no connect) pins must be connected to ground. moisture-sensitive packages are shipped from the factory dry-packed. handling instructions listed on the package label must be followed to prevent damage during reflow. refer to the ip c/jedec j-std-020 standard for moisture-sensitive device (msd) classifications. absolute maximum ratings stresses above the ratings listed below can cause perman ent damage to the IDT1338. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended dc operating conditions (v cc = v cc(min) to v cc(max) , ta = -40c to +85c, unless otherwise noted. typical values are at v cc = 3.3 v, ta = +25c, unless otherwise noted.) (note 1) item rating voltage range on any pin relative to ground -0.3 v to +6.0 v storage temperature -55 to +125 ? c soldering temperature 260 ? c parameter symbol min. typ. max. units ambient operating temperature t a -40 +85 ? c v bat input voltage, note 2 v bat 1.3 3.0 3.7 pull-up resistor voltag e (sqw/out), note 2 v pu 5.5 v logic 1, note 2 v ih 0.8 v cc v cc + 0.3 v logic 0, note 2 v il -0.3 +0.2 v cc v supply voltage IDT1338-18 v cc v pf 1.8 5.5 v IDT1338-31 v pf 3.3 5.5 power fail voltage IDT1338-18 v pf 1.40 1.62 1.71 v IDT1338-31 2.45 2.7 2.97
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 12 IDT1338 rev s 111214 dc electrical characteristics (v cc = v cc(min) to v cc(max) , ta = -40c to +85c, unless otherwise noted. typical values are at v cc = 3.3 v, ta = +25c, unless otherwise noted.) (note 1) dc electrical characteristics (v cc = 0v, ta = -40c to +85c, unless otherwise noted. typical values are at v bat = 3.0 v, ta = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min. typ. max. units input leakage i li note 3 1 a i/o leakage i lo note 4 1 a sda logic 0 output i olsda v cc > 2 v; v ol = 0.4 v 3.0 ma v cc < 2 v; v ol = 0.2 v cc 3.0 sqw/out logic 0 output i olsqw v cc > 2 v; v ol = 0.4 v 3.0 ma 1.71 v < v cc < 2 v; v ol = 0.2 v cc 3.0 ma 1.3 v < v cc < 1.71 v; v ol = 0.2 v cc 250 a active supply current (note 5) i cca IDT1338-18 7.5 15 a IDT1338-31; v cc < 3.63 v 12 20 IDT1338-31; 3.63 v < v cc < 5.5 v 14 25 standby current (note 6) i ccs IDT1338-18 1 2 a IDT1338-31; v cc < 3.63 v 1 2 IDT1338-31; 3.63 v < v cc < 5.5 v 25 v bat leakage current ( v cc active) i batlkg 25 100 na parameter symbol conditions min. typ. max. units v bat current (osc on); v bat =3.7 v, sqw/out off i batosc1 note 7 800 1200 na v bat current (osc on); v bat =3.7 v, sqw/out on i batosc2 note 7 1025 1400 na v bat data-retention current (osc off); v bat =3.7 v i batdat note 7 120 300 na
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 13 IDT1338 rev s 111214 ac electrical characteristics (v cc = v cc(min) to v cc(max) , ta = -40c to +85c) (note 1) warning: negative undershoots below -0.3 v while the device is in battery-backed mode may cause loss of data. note 1 : limits at -40c are guaranteed by design and are not production tested. note 2 : all voltages referenced to ground. note 3 : scl only. note 4 : sda and sqw/out. note 5 : i cca ?scl clocking at max frequency = 400 khz. note 6 : specified with the i 2 c bus inactive. parameter symbol conditions min. typ. max. units scl clock frequency f scl fast mode 100 400 khz standard mode 0 100 bus free time between a stop and start condition t buf fast mode 1.3 s standard mode 4.7 hold time (repeated) start condition, note 8 t hd:sta fast mode 0.6 s standard mode 4.0 low period of scl clock t low fast mode 1.3 s standard mode 4.7 high period of scl clock t high fast mode 0.6 s standard mode 4.0 setup time for a repeated start condition t su:sta fast mode 0.6 s standard mode 4.7 data hold time (notes 9, 10) t hd:dat fast mode 0 0.9 s standard mode 0 data setup time (note 11) t su:dat fast mode 100 ns standard mode 250 rise time of both sda and scl signals (note 12) t r fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 1000 fall time of both sda and scl signals (note 12) t f fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 300 setup time for stop condition t su:sto fast mode 0.6 s standard mode 4.0 capacitive load for each bus line (note 12) c b 400 pf i/o capacitance (sda, scl) c i/o note 13 10 pf oscillator stop flag (osf) delay t osf note 14 100 ms
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 14 IDT1338 rev s 111214 note 7 : measured with a 32.768 khz crystal on x1 and x2. note 8 : after this period, the first clock pulse is generated. note 9 : a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 10 : the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 11 : a fast-mode device can be used in a standard-mode system, but the requirement t su:dat > to 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su:dat = 1000 + 250 = 1250 ns before the scl line is released. note 12 : c b ?total capacitance of one bus line in pf. note 13 : guaranteed by design. not production tested. note 14 : the parameter t osf is the period of time the oscillator must be stopped for the osf flag to be set over the voltage range of 0.0v < v cc < v cc max and 1.3 v < v backup < 3.7 v. timing diagram
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 15 IDT1338 rev s 111214 typical operating characteristics ibat vs vbat (IDT1338-31) 494 534 574 614 654 694 734 1.3 1.8 2.3 2.8 3.3 vbat (v) supply current (na) sqwe=1 sqwe=0 icc vs vcc (IDT1338-31) 0 5 10 15 20 25 2.73.23.74.24.75.2 vcc (v) supply current (ua) scl=400khz scl=0hz ibat vs temperature 400 500 600 700 800 -40-20 0 20406080 temperature (c) ibat (na) sqwe=1 sqwe=0 oscillator frequency vs supply voltage 32767.750000 32767.800000 32767.850000 32767.900000 32767.950000 2.7 3.2 3.7 4.2 4.7 5.2 oscillator s upply voltage (v) frequency (hz) freq
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 16 IDT1338 rev s 111214 thermal characteristics for 8msop thermal characteristics for 8soic thermal characteristics for 16soic parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 95 ? c/w thermal resistance junction to case ? jc 48 ? c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 150 ? c/w ? ja 1 m/s air flow 140 ? c/w ? ja 3 m/s air flow 120 ? c/w thermal resistance junction to case ? jc 40 ? c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 120 ? c/w ? ja 1 m/s air flow 115 ? c/w ? ja 3 m/s air flow 105 ? c/w thermal resistance junction to case ? jc 58 ? c/w
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 17 IDT1338 rev s 111214 marking diagram (8 msop) marking diagram (8 soic) notes: 1. ?$? is the assembly mark code. 2. ?**? is the lot sequence. 3. ?yyww? is the last two digits of the year and week that the part was assembled. 4. ?g? denotes rohs compliant package. 5. ?i? denotes industrial grade. 6. bottom marking: lot number. marking diagram (16 soic) 38gi yyww$ IDT1338-31dvgi 18gi yyww$ IDT1338-18dvgi IDT1338 -31dcgi yyww$ 14 5 8 IDT1338-31dcgi IDT1338 -18dcgi yyww$ 14 5 8 IDT1338-18dcgi 1 8 9 16 idt 1338ac-31 srgi yyww**$ IDT1338ac-31srgi 1 8 9 16 idt 1338ac-18 srgi yyww**$ IDT1338ac-18srgi
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 18 IDT1338 rev s 111214 package outline and package dimensions (8-pin soic, 150 mil. body) package dimensions are kept current with jedec publication no. 95 index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c ? c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 ? 0 ? 8 ? 0 ? 8 ?
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 19 IDT1338 rev s 111214 package outline and package dimensions (8-pin msop, 3.00 mm body) package dimensions are kept current with jedec publication no. 95 index area 1 2 8 d e1 e seating plane a 1 a a 2 e - c - b aaa c ? c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a--1.10--0.043 a1 0 0.15 0 0.006 a2 0.79 0.97 0.031 0.038 b 0.22 0.38 0.008 0.015 c 0.08 0.23 0.003 0.009 d 3.00 basic 0.118 basic e 4.90 basic 0.193 basic e1 3.00 basic 0.118 basic e 0.65 basic 0.0256 basic l 0.40 0.80 0.016 0.032 ? 0 ? 8 ? 0 ? 8 ? aaa - 0.10 - 0.004
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 20 IDT1338 rev s 111214 package outline and package dimensions (16-pin soic, 300 mil body) package dimensions are kept current with jedec publication no. 95 index area 1 2 16 d e1 e seating plane a 1 a a 2 e - c - b aaa c ? c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a -- 2.65 -- 0.104 a1 0.10 -- 0.0040 -- a2 2.05 2.55 0.081 0.100 b 0.33 0.51 0.013 0.020 c 0.18 0.32 0.007 0.013 d 10.10 10.50 0.397 0.413 e 10.00 10.65 0.394 0.419 e1 7.40 7.60 0.291 0.299 e 1.27 basic 0.050 basic l 0.40 1.27 0.016 0.050 ? 0 ? 8 ? 0 ? 8 ? aaa - 0.10 - 0.004
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 21 IDT1338 rev s 111214 ordering information the IDT1338 packages are rohs compliant. packages wi thout the integrated cr ystal are pb-free; pack ages that include the integrated crystal (as designated with a ?c? before the dash number) may incl ude lead that is exempt under rohs requirements. the lead fini sh is jesd91 category e3. ?a? is the device revision designator and wi ll not correlate to th e datasheet revision. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 1338-18dvgi see page 17 tubes 8-pin msop -40 to +85 ? c 1338-18dvgi8 tape and reel 8-pin msop -40 to +85 ? c 1338-18dcgi tubes 8-pin soic -40 to +85 ? c 1338-18dcgi8 tape and reel 8-pin soic -40 to +85 ? c 1338ac-18srgi tubes 16-pin soic -40 to +85 ? c 1338ac-18srgi8 tape and reel 16-pin soic -40 to +85 ? c 1338-31dvgi tubes 8-pin msop -40 to +85 ? c 1338-31dvgi8 tape and reel 8-pin msop -40 to +85 ? c 1338-31dcgi tubes 8-pin soic -40 to +85 ? c 1338-31dcgi8 tape and reel 8-pin soic -40 to +85 ? c 1338ac-31srgi tubes 16-pin soic -40 to +85 ? c 1338ac-31srgi8 tape and reel 16-pin soic -40 to +85 ? c
IDT1338 real-time clock with battery backed non-volatile ram rtc idt? real-time clock with battery backed non-volatile ram 22 IDT1338 rev s 111214 revision history rev. originator date description of change a j. sarma 01/29/08 new device. preliminary release. b j.sarma 03/28/08 added new note to part ordering information pertaining to rohs compliance and pb-free devices. c j.sarma 04/03/04 combined -3 and -33 parts to -31 d j.sarma 05/19/08 the part number for 16pin rohs complaint part has now changed from IDT1338c-31sogi to IDT1338c-31sri and the IDT1338c-18sogi changed to IDT1338c-18sri e j.sarma 10/29/08 f j.sarma 11/10/08 updated block diagram; typical operating characteristics charts. g j.sarma 11/13/08 updated graphs in ?typical operating characteristics; added ?typical operating circuit? diagram h j.sarma 11/18/08 updated graphs in ?typical operating characteristics; updated block diagram; added ?battery backed? to device title. i j.sarma 12/02/08 updated typical operating characteristics graphs; added marking diagrams. j 11/10/09 added ?handling, pcb layout, and assembly? section. k s.s. 03/29/10 added ?timeout? paragraph on page 8. l l larsen 04/13/11 updated supply current speficiations m s.s. 09/22/11 changed ? v cc fall time; v pf(max) to v pf(min) ? spec from 300 s min. to 1ms min. (table 2, ?power-up/down characteristics) n s.s. 10/17/11 added separate item for tvccf in ?powe r-up/down conditions? table for 1338-31; 300 s min. p j. chao 09/20/12 1. moved all from fab4 to tsmc. qa requested change in the marking of only the 16-pin soic device with internal crystal to add "a" due to the fact that tsmc uses a different crystal than fab4. notification of a change in orderables was initiated with pcn a1208-06. 2. updated 16-pin soic marking diagram and ordering information to include "a". q j. chao 12/10/12 updated orderable parts - added ?g? to 16-pin soic parts with sri/sri8. new part numbers for 16-pin soic will read as srgi and srgi8. r j. chao 02/07/13 1. changed the vih min value to 0.8vcc and the vil max value to +0.2vcc on page 11. this is based on new data taken on tsmc samples (old data was from fab 4). 2. the ibatdat current on page 12 should change from 10na to 120na (typ) and from 100na to 300na (max) per latest characterization data from tsmc. r j. chao 03/10/14 changed tvccf min value from 300s to 3ms. added associated note. s rdw 11/12/14 updated device markings.
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